Mechanical Design Engineer with 14 years experience in Electronic Packaging of Power Electronic Module. Expertise in design and development of Electronic Modules from Conceptual to Manufacturing. Experienced in Design, Wafer Fab, Packaging and Assembly of Semiconductor chips and module for high reliability application. Filed three patents with US Patent office. Licensed as a California Professional Engineer.

Senior Project Engineer

• Design and develop custom hybrid module for space level component and high density memory module via die/package stacking, micro vias and rigid-flex for military application
• Design and develop 2.5 inch Solid State Hard Drive for ruggedize environment (including pyrotechnic shock environment)

• Provided process development, finite element anlysis and failure anlysis support to ensure completion of project

Science Application International Corp – Torrance, CA

December 05 - May 07

Staff Scientist

• Analyzed thermal model for Lithium-ion battery module on Hybrid Diesel-Electric Combat Vehicle for the US Army (part of Future Combat System Manned Ground Vehicle for TARDEC) which resulted in an thermal improvement for the 70%-30% Charge-Discharge cycle).
• Analyzed Heat Exchanger software module for VITMAC 6.1 (Vehicle Intergrated Thermal Management Analysis Code for NASA).
• Provided recommendations for bench test of a 3 phase bridge IGBT module for motor drive of Hybrid Diesel-Electric Vehicle.

Mechanical / Electronic Package Design Engineer

• Designed and developed Multi chips modules (Chip & Wires and SMD) with the goal of reducing electrical inductance, minimizing EMI effect and Design for Manufacturing.
• Coordinated design and manufacturing activities of Engineering Conceptual phase and Design Validation phase across US, Mexico and Europe to deliver to a Japanese customer.
• Searched for new materials to improve thermal and structural performance of Automotive Power Module which resulted in two patents filed.
• Selected and evaluated appropriate technology for project such as DBC (Alumina, Aluminum Nitrite and Silicon Nitrite), IMS, Al-SiC, Silver Epoxy, Silver Silicones, Insert Molded Lead Frame, Thick Film ceramics, Laser Trimmable resistor, Lead-free Solder, Wirebonding, Forged heat sink, and Silicone adhesive for thermal performance with high voltage isolation.
• Performed thermal analysis (steady state and transient) and mechanical structural stress analysis (linear, non-linear and creep) to improve performance of Electronic Modules via Finite Element Analysis using ANSYS and Design Space.
• Verify thermal analysis prediction (steady state and transient) via Flir Infrared Camera video capture and Thermocouple attachment reading.

Product Engineer

• Coordinated and introduced three new derivative products (TO-220 discrete devices) of Gen 3 High Voltage HEXFET between design, wafer fabrication, assembly and reliability qualification.
• Ensured New Products passed reliability tests via 8D problem solving process implementation.
• Perform preliminary failure analysis of products that has failure in HTRB, HTGB, THB, Autoclave, Thermal shock, Power cycle and moisture ingression.

Rotation Engineer

• Performed benchmark comparison of IR MOSFET versus Motorola, Siliconix, ST and Harris MOSFET, which resulted in upper management decision to shrink MOSFET chip to reduce cost in wafer.
• Performed Finite Element Analysis on Power Train Motor Drive products to improve mechanical and thermal performance.
• Improved electrical test yield on TO-220 assembly lines by identifying and reduced false rejects.
  

Bachelor of Science, Mechanical Engineering 1995

University of California, Los Angeles

ANSYS FEA, Design Space FEA, Solid Edge CAD, SolidWorks, AutoCAD, Havard Thermal TAS, Sinda 3D, Design of Experiment, Semiconductor Processing class.

Patents:

• Pin Fin Heat sink for channeling airflow for high power device (US Patent App-20060021736)

• Non-Isolated Heat sink for Power Module (US Patent-7042730)

• Linear Fan Controller Module for HVAC application (Filing)

• Adaptable Planar Array Connection process for DRAM Chip Stacking (Filing)

Paper: